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Digital Verification Engineer in Austin, TX at Eliassen Group

Date Posted: 4/9/2019

Job Snapshot

  • Employee Type:
  • Location:
    Austin, TX
  • Job Type:
  • Experience:
    Not Specified
  • Date Posted:

Job Description

Our industry leading client is in search of an experienced Verification Engineer to come in and hit the ground running.  This client prides themselves on remaining at the forefront of Energy Efficiency and ultra-low power.

As a Digital Verification Engineer, you will be responsible for:

  • Verify modules in the digital and analog subsystem
  • Work closely with digital and analog team to review and verify modules at a unit and/or SoC level using C based test cases, UVM agents or low level stimulus
  • Develop test plan, coverage plans for modules
  • Document in YAML based system
  • Perform coverage analysis, assertion creations for target modules
  • Develop test cases for modules that can be regressed and ported to other environments, such as chip level, validation environments, FPGA environments
  • Develop BFM modules to stimulate modules using verilog, C and UVM
  • Run gate level regressions in a full chip environment
  • Develop and run test cases in FPGA based system

Required Qualifications:

  • Knowledge and experience verifying RTL based designs in an RTL or gate environment
  • Knowledge and experience with UVM
  • Knowledge and experience with C code development
  • Knowledge and experience with coverage analysis and optimization
  • Knowledge and experience using linux based systems, including tools such as git, perl, make, TCL

Key Skills:

  • Able to develop modules and run test cases using C code and UVM/Verilog
  • Must have experience with verification of power domains, written test plans, augment test plans, coverage analysis(optimization), sequence of power domains.
  • An individual with broad/deep knowledge of CPF (Common Power Format) are very strong candidates

This opportunity is a contract-to-perm opportunity with optional benefits including Health, Medical, Dental, Vision, 401K, etc.

Key Terms: Verification Engineer, Digital Verification, UVM, Verilog, CPF, Common Power Format

Job ID: 318006

About Eliassen Group:

Eliassen Group provides strategic talent solutions to drive our clients’ innovation and business results. Leveraging over 30 years of success, our expertise in IT staffing, Agile consulting, creative services, managed services, and life sciences enables us to partner with our clients to execute their business strategy and scale effectively. Headquartered in Reading, MA and with offices from coast to coast, Eliassen Group offers local community presence, deep networks, as well as national reach. For more information, visit

Eliassen Group is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.

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